$ loading_
Query elaborated SystemVerilog and gate-level netlist structure with real connectivity.
Copy the install command and let the AI configure it · recommended for beginners
No copy-paste install info for "naja-scope" yet — see the docs or source repo.
Query the real driver of net rst_n in this design, and explain which module or instance it comes from across hierarchy.
Returns the net's driver relationship and explains its source using elaborated hierarchical connectivity.
List which submodules are instantiated by module alu_top and show the hierarchy.
Provides an instantiation list and hierarchy derived from the design structure, not from source-text matching.
Find which registers are in the fanin cone of signal data_out and indicate their hierarchy locations.
Returns the registers in the fanin cone with hierarchy locations, reflecting real post-elaboration connectivity.
Chip or RTL developers can query the real drivers and connections of a net in a complex design instead of manually reading many RTL files. The results are based on the elaborated netlist structure, which is better for cross-hierarchy analysis.
When you need to quickly understand which submodules a module instantiates, this tool can show the real structural hierarchy directly. That is closer to the actual elaborated design than plain text search.
During design analysis or debugging, you can query the registers contained in a signal's fanin cone. It is useful when you need to understand timing-related structure from real connectivity.
It is an MCP server for elaborated SystemVerilog and gate-level netlists. It lets agents query design structure such as what drives a net, what a module instantiates, and which registers are in a fanin cone.
Its answers come from najaeda's netlist engine, so they reflect real post-elaboration hierarchical connectivity rather than source-text matches. This makes it more direct for cross-hierarchy connectivity analysis.
The provided information only says it is an MCP server and that it relies on najaeda's netlist engine. For exact installation steps, runtime requirements, or input formats, see the source repository.
Provides a live codebase architecture model for analysis and dependency tracing.
Control a bench oscilloscope over LAN for hardware debugging and validation.
Run comprehensive network scans and port discovery through an MCP server.
Collect system info, run network scans, and extend workflows with custom tools.
Run connectivity checks, batch diagnostics, and pcap analysis to troubleshoot networks.
Analyze MCP tool security risks, detect malicious behavior, and provide risk scores.